1. Field of the Invention
The invention relates to memories, and more particularly, to a method of memory management capable of increasing memory efficiency.
2. Description of the Related Art
Of all system-on-chips (SOCs), memory controllers process all data transfers and instruction scheduling. Thus, increasing memory efficiency is a determining factor for computing performance.
Currently, main memories, like SDRAM, DDR-DRAM, DDR2-DRAM and DDR3-DRAM, are usually divided into multiple banks where each bank consists of a number of rows. A row is then divided into columns. Based on this architecture, certain inherent limitations of memories result in a reduced memory efficiency. First, a bank conflict occurs while consecutive access requests are to the same bank but different rows (or pages). The total bank conflict time is the total of the “activate to read” (tRCD) latency plus the “read to pre-charge” (tRPD) latency plus the “pre-charge to activate” (tRp) latency, or the “activate to activate command period” (tRC), whichever timing constraint is longer. On the other hand, while consecutive access requests target different banks, the bank conflict will not occur and the system no longer needs to wait for the tRC latency.
FIG. 1 is a diagram showing two consecutive executed access requests targeting the same bank. For simplicity, assuming that memory 100 consists of only two banks B0, B1 and a Mth access request (such as a read request) targeting from page 2 to page 1 of the bank B0 has been already executed by a memory controller (not shown). Then the starting address of a subsequent (Nth) access request resides in page 1 of the bank B0. At this moment, the bank conflict occurs since consecutive access requests are being made to the same bank B0. Due to the bank conflict, the memory controller has to issue a pre-charge command to de-activate the bank B0. Then an activate command to open the page 1 of the bank B0 and, finally, a read command to the bank B0 in order to complete the Nth access request.
The second inherent limitation of memories resulting in a reduced memory efficiency is the write-to-read turnaround conflict. To the data bus, the read operation and the write operation result in opposite directions of data flow; therefore, it takes time to reverse the direction of the data bus while two consecutive access requests with different access types are being executed. In addition, refresh operations and command conflicts may also affect memory efficiency and thus will not be described since they are not the subject of the specification. In addition, the bank conflict latency is much longer than the write-to-read turnaround conflict latency. Thus, it is necessary to reduce the probability of bank conflicts.
In virtue of the importance of memory efficiency and both the real-time access characteristic and the massive data transfer characteristic of multi-media video and audio products, the invention provides a method of memory management capable of improving memory efficiency and meeting the requirements of the multi-media video and audio products.